20% growth then 20% again still seems pretty good to me though. I guess compounded that is a 44% increase N3 to A14 which also starts to look much better if you zoom out a bit. I mean 44% more density since a few years ago seems, if not massive, not insignificant, like you will definitely notice it.
If we exclude short-term shortages then no. The cost to make a wafer hasn't really changed. Larger wafers improved costs but that's about it AFAIK.
Feature sizes have been shrinking unevenly for two decades now combined with the overall slowdown in improvements. Transistors themselves are FinFET geometry and something like 15-30 atoms thick and maybe 80-100 across. There ain't much juice left to squeeze in terms of size but perhaps we'll figure out how to reduce leakage (heat).
Physics hates the very large and the very small. The large get the tyranny of volume scaling + general relativity. The small have their entire concept of reality smashed by quantum mechanics.
The cost-per-transistor used to fall as density increased (Moore's Law), but has now basically flattened off.
As each generation of lithography tech (DUV -> EUV -> High-NA EUV) gets pushed to the limit, it becomes necessary to use multiple etching steps per layer (higher cost, less wafers-per-minute) where previously one had been enough, then the next generation (e.g. EUV vs DUV) resets that to one step, then that becomes two ...
The trouble is that each new generation of tech costs considerably more than the one it replaces, both in terms of machine cost and operational cost, so the overall trend seems to have become fairly flat.
It's hard to tell because AI has pushed up costs. IE. Chip fab margins are increasing.
But generally, I think it's even or increasing $/transistor for each node. I'd guess that A14 would have been 20% more expensive than N2 regardless or AI or not.
It probably is still worth it because you're also getting 20-30% better power efficiency - which is a big deal for data center chips.
A lot of that is the lack of SRAM scaling. There’s still quite a bit of improvements in the back end (metal traces). That aside, if foundries adopted say a 1T-1C SRAM we’d see a pretty rapid density doubling
Is 1T1C SRAM a technological thing or does it mean "persuade designers to use DRAM in the many cases where the retention contract could be timeboxed with a bit of extra thought and cross-team haggling"?
The reality is often going to be much worse than TSMC's N2 -> A14 "mixed design" 20% density increase marketing spin.
Apparently the N2 -> A14 density increase for logic is 23% (Tom's Hardware), and about 0% for both SRAM and analog.
Both CPUs and GPUs devote considerable space to SRAM (registers & cache), and are 50% or less logic, so for them the density increase will be more like 10% rather than TSMC's 20% marketing number.
MRAM is 1T, non-volatile and supposedly has nanosecond-scale write times so it naively seems like it'd be an ideal SRAM replacement. But I guess shrinking MTJ is more difficult than other components or there are some other limitations.
Aka eDRAM? It was a thing back on 14nm node, but AFAIR not so much anymore. The 1C part is hard to get right in a way that is compatible with a logic process.
Yes but considering N10 was fabricated with DUV lithography right before the shift to EUV I'm not sure how fair that comparison is. That being said the density scaling of N10 nodes compared to predecessors using the same lithography technique was much higher than we have seen since with the EUV nodes. Density scaling is the most meaningful comparison metric, but it doesn't take into account additional technology developments.
What's wild is that the mirrors used in the EUV machines are smooth to a level of deviation even smaller that the feature size of the gates being etched.
These mirrors are up to a couple of feet in diameter, with an average smoothness deviation of less than the width of an atom, maximum bump size of 1nm or less. They like to point out that if scaled up to the size of Germany (Zeiss makes them), the biggest surface defect would still only be 0.1mm!
I did find it funny recently when Huawei when talking about its folded logic say the Vertical Bonding Pitch's are every 15,000 angstroms. It is a very fancy way of saying an interconnect every 1.5 microns.
In simpler terms, the SRAM density improved by 2.9% (according to ChatGPT). Which is better than it sounds, because SRAM had reached a wall, in terms of density gains, and, chips can be dominated by SRAM in terms of surface area, so this can mean a lot more room for logic, even though that is also getting considerably denser.
Or AMD’s putting sram on a separate chip. I’m surprised they didn’t go there yet except for extra L3 instead of all of it. At some point the costs will shift the decisions.
IEDM is more or less the most prestigious conference on semiconductor devices. Hard to get a more reliable source than a TSCM-affiliated paper from IEDM.
cat /usr/share/X11/locale/en_US.UTF-8/Compose | grep Å
<dead_abovering> <A> : "Å" Aring # LATIN CAPITAL LETTER A WITH RING ABOVE
<Multi_key> <o> <A> : "Å" Aring # LATIN CAPITAL LETTER A WITH RING ABOVE
<Multi_key> <asterisk> <A> : "Å" Aring # LATIN CAPITAL LETTER A WITH RING ABOVE
<Multi_key> <A> <asterisk> : "Å" Aring # LATIN CAPITAL LETTER A WITH RING ABOVE
<Multi_key> <A> <A> : "Å" Aring # LATIN CAPITAL LETTER A WITH RING ABOVE
I was laughing at the expected expectation of universally working UTF-8 just because it's 2026 when I read that. Soooo many things just do not work with UTF-8 as expected. I'm looking at MS Excel with heavy side eye
No one seem to notice that TSMC has kept its timelines inspite if incredibly advance manufacuring,robotics,materials engineering,semi conductor engineering..and many more requirememts.
Chip density increase is slowing down. Since N10, density scaling has been 60-80%. N3 to N2 is only 20%. And now N2 to A14 is also only 20%.
20% growth then 20% again still seems pretty good to me though. I guess compounded that is a 44% increase N3 to A14 which also starts to look much better if you zoom out a bit. I mean 44% more density since a few years ago seems, if not massive, not insignificant, like you will definitely notice it.
Yes but it takes 8 years to have the same scaling as 2 years before.
Is the increase in wafer cost higher than the density increase? If so, that means that the cost per transistor is also going up.
If we exclude short-term shortages then no. The cost to make a wafer hasn't really changed. Larger wafers improved costs but that's about it AFAIK.
Feature sizes have been shrinking unevenly for two decades now combined with the overall slowdown in improvements. Transistors themselves are FinFET geometry and something like 15-30 atoms thick and maybe 80-100 across. There ain't much juice left to squeeze in terms of size but perhaps we'll figure out how to reduce leakage (heat).
Physics hates the very large and the very small. The large get the tyranny of volume scaling + general relativity. The small have their entire concept of reality smashed by quantum mechanics.
The cost-per-transistor used to fall as density increased (Moore's Law), but has now basically flattened off.
As each generation of lithography tech (DUV -> EUV -> High-NA EUV) gets pushed to the limit, it becomes necessary to use multiple etching steps per layer (higher cost, less wafers-per-minute) where previously one had been enough, then the next generation (e.g. EUV vs DUV) resets that to one step, then that becomes two ...
The trouble is that each new generation of tech costs considerably more than the one it replaces, both in terms of machine cost and operational cost, so the overall trend seems to have become fairly flat.
I think the cost per transistor has gone slightly upwards, it bottomed out a few years ago.
It's hard to tell because AI has pushed up costs. IE. Chip fab margins are increasing.
But generally, I think it's even or increasing $/transistor for each node. I'd guess that A14 would have been 20% more expensive than N2 regardless or AI or not.
It probably is still worth it because you're also getting 20-30% better power efficiency - which is a big deal for data center chips.
A lot of that is the lack of SRAM scaling. There’s still quite a bit of improvements in the back end (metal traces). That aside, if foundries adopted say a 1T-1C SRAM we’d see a pretty rapid density doubling
Is 1T1C SRAM a technological thing or does it mean "persuade designers to use DRAM in the many cases where the retention contract could be timeboxed with a bit of extra thought and cross-team haggling"?
The reality is often going to be much worse than TSMC's N2 -> A14 "mixed design" 20% density increase marketing spin.
Apparently the N2 -> A14 density increase for logic is 23% (Tom's Hardware), and about 0% for both SRAM and analog.
Both CPUs and GPUs devote considerable space to SRAM (registers & cache), and are 50% or less logic, so for them the density increase will be more like 10% rather than TSMC's 20% marketing number.
MRAM is 1T, non-volatile and supposedly has nanosecond-scale write times so it naively seems like it'd be an ideal SRAM replacement. But I guess shrinking MTJ is more difficult than other components or there are some other limitations.
MRAM is more like 100ns, but yeah Intel actually offers this as part of their 16nm foundry process
> 1T-1C SRAM
Aka eDRAM? It was a thing back on 14nm node, but AFAIR not so much anymore. The 1C part is hard to get right in a way that is compatible with a logic process.
It gets confusing...
eDRAM isn't the same as 1T-SRAM, which isn't quite the same as 1T-1C SRAM...
But overall they run into the same problems that you mention; it's just too hard to get a capacitor in play.
There is Zeno Semi's Bi-SRAM, buuuut it hasn't seemed to catch on for one reason or another.
> Bi-SRAM
Looks cool, but isn't it by definition planar process-only, no FinFET for you?
Yes but considering N10 was fabricated with DUV lithography right before the shift to EUV I'm not sure how fair that comparison is. That being said the density scaling of N10 nodes compared to predecessors using the same lithography technique was much higher than we have seen since with the EUV nodes. Density scaling is the most meaningful comparison metric, but it doesn't take into account additional technology developments.
Between N2 and A14 should sit A16.
A16 is a half node. It is a derivative of N2 family.
I can’t believe we’re talking Angstroms already.
What's wild is that the mirrors used in the EUV machines are smooth to a level of deviation even smaller that the feature size of the gates being etched.
These mirrors are up to a couple of feet in diameter, with an average smoothness deviation of less than the width of an atom, maximum bump size of 1nm or less. They like to point out that if scaled up to the size of Germany (Zeiss makes them), the biggest surface defect would still only be 0.1mm!
I did find it funny recently when Huawei when talking about its folded logic say the Vertical Bonding Pitch's are every 15,000 angstroms. It is a very fancy way of saying an interconnect every 1.5 microns.
They should just say every 7 silicon atoms at that point.
7500 surely? But yeah at this point I feel like the diameter of a silicon atom would make for a better unit of measure.
Oh right i was thinking the feature size (about that many namometers not microns)
In simpler terms, the SRAM density improved by 2.9% (according to ChatGPT). Which is better than it sounds, because SRAM had reached a wall, in terms of density gains, and, chips can be dominated by SRAM in terms of surface area, so this can mean a lot more room for logic, even though that is also getting considerably denser.
There's some hope of smaller SRAM in the future - https://raaam-tech.com/technology/ is a three-transistor SRAM.
It's not quite SRAM, it needs to be refreshed like DRAM. That's the main downside compared to SRAM but it's still very interesting.
Yes, the density vs power tradeoff could make a lot of sense in a few applications.
I wonder if it would start to make sense for SRAM caches to shrink (or not grow as fast) in favor of adding on chip DRAM cache at some tier.
Or AMD’s putting sram on a separate chip. I’m surprised they didn’t go there yet except for extra L3 instead of all of it. At some point the costs will shift the decisions.
They claim win + win*10:
> provides up-to 50% area reduction and reduced power consumption by a factor ten
This is exactly why Cerebras wafer chips aren’t even on N3. They stayed on N5. It is also why they are now stacking HBM onto the chip.
TSMC: https://www.tsmc.com/english/dedicatedFoundry/technology/log...
Not sure what this source is, but it looks sketchy.
IEDM is more or less the most prestigious conference on semiconductor devices. Hard to get a more reliable source than a TSCM-affiliated paper from IEDM.
Sorry, I got thrown off by the domain.
The source is the IEDM conference website where TSMC will be presenting the paper in Dec 2026
Whatever happened to the problem of electrons just hopping around since they are areas of probability rather than particles when you get small enough
Come on we're in the 21st century, UTF-8 is pervasive. Just call it "Å14" node.
I don't think it's a UTF-8 problem. It's just that most people don't have "Å" on their keyboard.
> most people don't have
Many people don't know.
Å - long press "a" on the ios keyboard and you get a whole list, slide your finger to the one you want, and let go.
tips in linux, remap altgr to compose and enjoy glyphs
Most people don’t have “é” on their keyboard, yet they still spell “fiancée”.
They only do if autocorrect allows it
Do they? Other than like the new yorker?
On mac this is just Opt + A
What's □14 node?
I was laughing at the expected expectation of universally working UTF-8 just because it's 2026 when I read that. Soooo many things just do not work with UTF-8 as expected. I'm looking at MS Excel with heavy side eye
"�14" does have a nice touch to it.
A14 is more in keeping with N2, and it is anyways just a name, not a measurement.
No one seem to notice that TSMC has kept its timelines inspite if incredibly advance manufacuring,robotics,materials engineering,semi conductor engineering..and many more requirememts.
I think its a miracle.
That’s why TSMC is indispensable for the global economy. No other foundry can produce advanced logic at scale like them.
They are extremely reliable.
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