The layers still need something to link together. You could try a board with as many MSPM0C1104 as you can fit on each side. I'm sure you could use the layers to make some esoteric interconnection map.
A dsbga-28 MSPM0G1106 might be better for using up the layers. 4.2mm^2 still so maybe 24 per square cm.
Shouldn't that have already been do-able? I know the The MOnSter 6502 is a thing. The 386 I have no idea about though, that's to far out of my wheel house.
A replica 386 would be impractically large - it's got around 275k transistors, compared to the 3.5k in the 6502. At the same scale as the MOnSter 6502, that'd be about a hundred square feet of PCB.
The number of layers isn't even remotely close to being a constraint. The real i386DX was manufactured on a process which only supported two metal layers, and a PCB version isn't subject to the same constraints as silicon.
Components like transistors usually have to go on the surface of a PCB. (While there are techniques for embedding components in a PCB, they're extraordinarily expensive and would not be feasible for a project like this one.)
> TOKYO, April 25, 2025 -- OKI Circuit Technology... OTC is seeking to establish mass production technology by October 2025 at its Joetsu Plant in Joetsu City, Niigata Prefecture
Dan, this is 2025! Not a Hacker News-worthy at the end of 2026.
Also, 124 layer PCB is ONLY 15% extra than the conventional 108 layer PCB. Incremental upgrade!
They state it's for HBM wafer inspection equipment:
OKI Group printed circuit board (PCB) company, has successfully developed 124-layer PCB technology for wafer inspection equipment designed for next-generation high bandwidth memory, such as HBM
Since the latest semiconductors process an enormous number of signals and the number of wafer-mounted chips increases due to process miniaturization, it is necessary to increase density and more layers on the PCBs used in inspection equipment.
In their linked semiconductor testing page[1], they mention conductive paste. So seems they test whole wafers by having the whole wafer put on such a PCB, using conductive paste instead of solder or similar, and the high layer count is then to be able to bring out all the connections (pins) from each chip to the testing circuits while maintaining the high signal integrity required for the high-speed signals.
HBM makes it worse since it is fast due to its very high bus width, 1024 bits wide, moving to 2048 bits wide[2]. So to test a HBM chip on a wafer before its cut and bonded to a GPU chip or such, you'd need to bring out those thousands of connections per chip on the wafer. Hence the need for so many layers compared to a regular PCB.
The number of levels of traces and gates laid out is an important aspect of how much sophistication and capability available to connect ICs on a pcb. You are laying out power and ground and communication. There are lots of other considerations like the complexity of what you can plan to layout using software. But you stack layers of traces to add capability. More layers is naively more capability.
So... at what point does someone re-create a 386 or 6501 but using only a motherboard, with no discrete circuits?
The layers still need something to link together. You could try a board with as many MSPM0C1104 as you can fit on each side. I'm sure you could use the layers to make some esoteric interconnection map.
A dsbga-28 MSPM0G1106 might be better for using up the layers. 4.2mm^2 still so maybe 24 per square cm.
Shouldn't that have already been do-able? I know the The MOnSter 6502 is a thing. The 386 I have no idea about though, that's to far out of my wheel house.
https://monster6502.com/
A replica 386 would be impractically large - it's got around 275k transistors, compared to the 3.5k in the 6502. At the same scale as the MOnSter 6502, that'd be about a hundred square feet of PCB.
The number of layers isn't even remotely close to being a constraint. The real i386DX was manufactured on a process which only supported two metal layers, and a PCB version isn't subject to the same constraints as silicon.
But in terms of rearranging the stack vertically; is that a possibility?
Components like transistors usually have to go on the surface of a PCB. (While there are techniques for embedding components in a PCB, they're extraordinarily expensive and would not be feasible for a project like this one.)
Interesting, thanks for the info.
> TOKYO, April 25, 2025 -- OKI Circuit Technology... OTC is seeking to establish mass production technology by October 2025 at its Joetsu Plant in Joetsu City, Niigata Prefecture
Dan, this is 2025! Not a Hacker News-worthy at the end of 2026.
Also, 124 layer PCB is ONLY 15% extra than the conventional 108 layer PCB. Incremental upgrade!
Can someone explain the implications of this?
They state it's for HBM wafer inspection equipment:
OKI Group printed circuit board (PCB) company, has successfully developed 124-layer PCB technology for wafer inspection equipment designed for next-generation high bandwidth memory, such as HBM
Since the latest semiconductors process an enormous number of signals and the number of wafer-mounted chips increases due to process miniaturization, it is necessary to increase density and more layers on the PCBs used in inspection equipment.
In their linked semiconductor testing page[1], they mention conductive paste. So seems they test whole wafers by having the whole wafer put on such a PCB, using conductive paste instead of solder or similar, and the high layer count is then to be able to bring out all the connections (pins) from each chip to the testing circuits while maintaining the high signal integrity required for the high-speed signals.
HBM makes it worse since it is fast due to its very high bus width, 1024 bits wide, moving to 2048 bits wide[2]. So to test a HBM chip on a wafer before its cut and bonded to a GPU chip or such, you'd need to bring out those thousands of connections per chip on the wafer. Hence the need for so many layers compared to a regular PCB.
That's my semi-informed take.
[1]: https://www.oki-otc.jp/en/products/test.html
[2]: https://www.nextpcb.com/blog/hbm-vs-gddr7-pcb-layout#pcb-hbm
The number of levels of traces and gates laid out is an important aspect of how much sophistication and capability available to connect ICs on a pcb. You are laying out power and ground and communication. There are lots of other considerations like the complexity of what you can plan to layout using software. But you stack layers of traces to add capability. More layers is naively more capability.
This article from Aug 2026 says 20 layers are for complex designs. https://www.pcbasic.com/blog/pcb-layers.html. So 124 layers looks like a huge increase.
Not my area, probably got it all wrong, hope this is useful.
The PCB itself often forms several different components these days.
Higher density chip packing is only one advantage. Unlikely going to see such things in cost-optimized consumer products. =3
OKI ? As in, my cellular scanner ?